Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.
A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. The 3D memory architecture also includes a stack of word lines horizontally arranged over a substrate, with vertical semiconductor channels that intersect the word lines. The intersection of a word line and a vertical semiconductor channel forms a memory cell.